The present application claims priority to Japanese Application(s) No(s). P2000-275695 filed Sep. 11, 2000, which application(s) is/are incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to methods for producing an electrode and a semiconductor device, more particularly relates to methods for producing an electrode formed in a small size and high density semiconductor device for mounting the same device and for producing a semiconductor device provided with the electrode.
2. Description of the Related Art
In the past, progress has been made in semiconductor processes to incorporate many kinds of functions into one chip to improve the performance. Because of the necessity of combining different processes, there was a tendency for the processing steps to become complicated, the number of steps to increase, the yield to decline, and the turn-around time (TAT) to increase.
Thereupon, in recent years, the practice has become to fabricate IC chips having different functions and to use packages of them to give the same performance as a single chip, i.e., to use a multi-chip module (MCM).
Specifically, there is the method of mounting chips on an organic or ceramic board called an interposer, on which interconnections are laid in advance, then connecting the pads of IC chips and pads of the interposer by wire bonding so as to form an interface among the IC chips. Alternatively, there is the method of forming bumps (projecting electrodes) on IC chips in advance by gold or solder, then matching and connecting the bumps with the pads of the interposer.
In the above methods of the related art, however, in order to secure good connections by the wire bonding or bumps, a connection area of not less than 50xc3x9750 xcexcm2 was needed for pads on the IC chip, and a pitch not less than 70 to 80 xcexcm was necessary to avoid contact with neighboring wires or bumps.
Therefore, due to the above rule, even if arranging pads all over the available area of an IC chip, the number of pads was limited to several hundred at most. Especially, with the wire bonding method, there was an unfavorable constraint that pads could be arranged only at the periphery of a chip.
As a result, it suffers from the disadvantage that the MCM method was not usable when over 1000 connections were required. In this case, the functions all had to be provided on a single chip.
In this way, in the methods of the related art, there was the disadvantage that the number of connections between chips was highly limited.
An object of the present invention is to provide a method for producing an electrode which enables over 1000 interconnections between chips, impossible in the related art, and enables fabrication of small electrodes with a high dimensional accuracy without being affected by the number of connections between chips.
Another object of the present invention is to provide a method for producing a semiconductor device provided with the electrode.
To attain the first object, according to a first aspect of the present invention, there is provided a method for producing an electrode for forming at least one electrode on a semiconductor chip on which semiconductor integrated circuit elements and an interconnection pattern are formed, comprising the steps of forming an insulating film on the interconnection pattern of the semiconductor chip, forming on the insulating film a mask layer having an opening at a position where the electrode is to be formed, removing the insulating film within the opening by using the mask layer as a mask to expose a portion of the interconnection pattern, forming a conductor layer on the exposed interconnection pattern and the mask layer, removing the conductor layer formed on the mask layer while leaving the conductor layer formed on the exposed interconnection pattern, and removing the mask layer.
For example, the step of forming the conductor layer comprises a step of forming the conductor layer by copper.
In this case, the method further comprises a step of forming a barrier film on the exposed interconnection pattern and the mask layer after exposing a portion of the interconnection pattern and before forming the conductor layer. The step of forming the conductor layer then comprises a step of forming the conductor layer on the barrier film, while the step of removing the conductor layer comprises a step of removing the barrier film and the conductor layer formed on the mask layer while leaving the barrier film and the conductor layer formed on the exposed interconnection pattern.
Preferably, the method further comprises a step of forming a protective film on the conductor layer after removing the mask layer.
To attain the above object, according to a second aspect of the present invention, there is provided a method for producing a semiconductor device comprising the steps of forming a semiconductor integrated circuit element on a substrate, forming an interlayer insulating film to cover the semiconductor integrated circuit element, forming a connection hole for connecting with the semiconductor integrated circuit element and an interconnection groove on the interlayer insulating film, burying the connection hole and the interconnection groove with a conductor layer to form an interconnection pattern, forming an insulating film on the interconnection pattern, forming a mask layer having an opening in the insulating film at a position where the electrode is to be formed, removing the insulating film within the opening by using the mask layer as a mask to expose a portion of the interconnection pattern, forming a conductor layer on the interconnection pattern and the mask layer, removing the conductor layer formed on the mask layer while leaving the conductor layer formed on the interconnection pattern, and removing the mask layer.
Further, in case of multi-layer interconnections, the method comprises, after forming the interconnection pattern and before forming the insulating film, a step of repeating a step of further forming an upper interlayer insulating film to cover the interconnection pattern; the step of forming a connection hole for connecting with the lower interconnection pattern and an interconnection groove in the interlayer insulating film; and the step of burying the connection hole and the interconnection groove by a conductor layer to form an upper interconnection pattern. Further, the step of forming an insulating film on the interconnection pattern comprises forming an insulating film on the uppermost interconnection pattern, while the step of exposing a portion of the interconnection pattern comprises exposing a portion of the uppermost interconnection pattern.
According to the methods for producing an electrode and a semiconductor device according to the present invention, in the formation of a circuits by repeating the steps of forming interlayer insulating films and interconnection patterns on a substrate formed with semiconductor integrated circuit elements, after an interconnection pattern is formed, an insulating film and a mask layer are formed, an opening having a reasonable diameter is formed at a position where the electrode is to be formed, the opening is buried with a conductor layer (the material of the interconnection), the mask layer is removed, and finally a projecting small electrode (micro-bump) is formed on the insulating film.
By this, a small electrode can be formed at a high dimensional accuracy in fabrication of a semiconductor device formed with semiconductor integrated circuit elements.
Further, when copper is used for the conductor layer, in order to prevent oxidation of the exposed portion, a protective film comprised of nickel or aluminum is formed.